| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | User-friendly environment for rapid design of logic circuits. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Supports hierarchical logic design. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Added a tool on fault analysis at the gate level of digital. Faults: Stuck-1, stuck-at-0. The technique allows injection of single stuck-at fault at the nodes of the circuit. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Improved interface between DSCH and Winspice. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Handles both conventional pattern-based logic simulation and intuitive on screen mouse-driven simulation. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with PSPICETM and WinSpiceTM). | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Generates a VERILOG description of the schematic for layout conversion. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Immediate access to symbol properties (Delay, fanout). | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Model and assembly support for 8051 and PIC 16F84 microcontrollers. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Sub-micron, deep-submicron, nanoscale technology support. | |
| ![](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tILv_FtN__vBxIZFUJA3HBgADb1U2DuDCCn2Kg7Uwo-5ijKYlo1Q9hXX9GUvK8nz4hXq1M6TxukGTu7YYbHCCuq9C3oK6Qsq9Qp2APOw=s0-d) | | Supported by huge symbol library |
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